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km432s2030c cmos sdram rev. 1.1 mar. '99 - 1 - 2m x 32 sdram revision 1.1 march 1999 512k x 32bit x 4 banks synchronous dram lvttl samsung electronics reserves the right to change products or specification without notice.
km432s2030c cmos sdram rev. 1.1 mar. '99 - 2 - revision 1.1 (march 12th, 1999) ? corrected typo in ordering information on page 3 revision 1.0 (march 8th, 1999) - final spec ? removed km432s2030c-z@cl2 part (125mhz@cl2) ? changed trdl from 1clk to 2clk for every clock frequency. for -6/7/8/10, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" revision 0.3 (march 5th, 1999) - preliminary spec revision 0.2 (february 13th, 1999) ? removed km432s2030c-7@cl2 part (115mhz@cl2) ? changed vdd condition of km432s2030c-8@cl2 from 3.135v to 3.0v~3.6v. ? changed ac characteristic table format ? add km432s2030c-z part. revision 0.1 (december 2nd, 1998) ? delete refresh information(4k/64ms) revision 0.0 (november 20th, 1998) ? define target specification. revision history
km432s2030c cmos sdram rev. 1.1 mar. '99 - 3 - the km432s2030c is 67,108,864 bits synchronous high data rate dynamic ram organized as 4 x 524,288 words by 32 bits, fabricated with samsung s high performance cmos technol- ogy. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ? 3.3v power supply ? lvttl compatible with multiplexed address ? four banks operation ? mrs cycle with address key programs -. cas latency (2 & 3) -. burst length (1, 2, 4, 8 & full page) -. burst type (sequential & interleave) ? all inputs are sampled at the positive going edge of the system clock ? burst read single-bit write operation ? dqm for masking ? auto & self refresh ? 15.6us refresh duty cycle general description features 512k x 32bit x 4 banks synchronous dram ordering information part no. max freq. interface package km432s2030ct-g/f6 166mhz lvttl 86 tsop(ii) km432s2030ct-g/f7 143mhz km432s2030ct-g/f8 125mhz km432s2030ct-g/f10 100mhz functional block diagram samsung electronics reserves the right to change products or specification without notice. * bank select data input register 512k x 32 512k x 32 s e n s e a m p o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register a d d r e s s r e g i s t e r r o w b u f f e r r e f r e s h c o u n t e r r o w d e c o d e r c o l . b u f f e r l r a s l c b r lcke lras lcbr lwe ldqm clk cke cs ras cas we dqm lwe ldqm dqi clk add lcas lwcbr 512k x 32 512k x 32 timing register
km432s2030c cmos sdram rev. 1.1 mar. '99 - 4 - pin configuration (top view) v dd dq0 v ddq dq1 dq2 v ssq dq3 dq4 v ddq dq5 dq6 v ssq dq7 n.c v dd dqm0 we cas ras cs n.c ba0 ba1 a10/ap a0 a1 a2 dqm2 v dd n.c dq16 v ssq dq17 dq18 v ddq dq19 dq20 v ssq dq21 dq22 v ddq dq23 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 v ss dq15 v ssq dq14 dq13 v ddq dq12 dq11 v ssq dq10 dq9 v ddq dq8 n.c v ss dqm1 n.c n.c clk cke a9 a8 a7 a6 a5 a4 a3 dqm3 v ss n.c dq31 v ddq dq30 dq29 v ssq dq28 dq27 v ddq dq26 dq25 v ssq dq24 v ss 86pin tsop (ii) (400mil x 875mil) (0.5 mm pin pitch)
km432s2030c cmos sdram rev. 1.1 mar. '99 - 5 - absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1 w short circuit current i os 50 ma permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : pin function description pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqm. cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disables input buffers for power down mode. a 0 ~ a 10 address row/column addresses are multiplexed on the same pins. row address : ra 0 ~ ra 10 , column address : ca 0 ~ ca 7 ba0,1 bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas , we active. dqm0 ~ 3 data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active. dq 0 ~ 31 data input/output data inputs/outputs are multiplexed on the same pins. v dd /v ss power supply/ground power and ground for the input buffers and the core logic. v ddq /v ssq data output power/ground isolated power supply and ground for the output buffers to provide improved noise immunity. nc no connection this pin is recommended to be left no connection on the device. capacitance (v dd = 3.3v, t a = 23 c, f = 1mhz, v ref = 1.4v 200 mv) pin symbol min max unit clock c clk 2.5 4 pf ras , cas , we , cs , cke, dqm c in 2.5 4.5 pf address c add 2.5 4.5 pf dq 0 ~ dq 31 c out 4.0 6.5 pf
km432s2030c cmos sdram rev. 1.1 mar. '99 - 6 - dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c) parameter symbol test condition cas latency version unit note -6 -7 -8 -10 operating current (one bank active) i cc1 burst length = 1 t rc 3 t rc (min) i ol = 0 ma 3 140 130 130 115 ma 1 2 - - 130 115 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 15ns 2 ma i cc2 ps cke & clk v il (max), t cc = 2 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 20 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 10 ma active standby current in power-down mode i cc3 p cke v il (max), t cc = 15ns 3 ma i cc3 ps cke & clk v il (max), t cc = 3 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 30 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 20 ma operating current (burst mode) i cc4 i ol = 0 ma page burst 2 banks activated 3 200 180 150 130 ma 1 2 - - 130 110 refresh current i cc5 t rc 3 t rc (min) 3 200 180 160 150 ma 2 2 - - 160 150 self refresh current i cc6 cke 0.2v 2 ma 3 450 ua 4 1. measured with outputs open. 2. refresh period is 64ms. 3. km432s2030ct-g** 4. km432s2030ct-f** notes : dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) parameter symbol min typ max unit note supply voltage v dd , v ddq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 v ddq +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current (inputs) i il -1 - 1 ua 3 input leakage current (i/o pins) i il -1.5 - 1.5 ua 3,4 1. v ih (max) = 5.6v ac.the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ddq , input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v v out v ddq. 5. the vdd condition of km432s2030c-6 is 3.135v~3.6v. notes :
km432s2030c cmos sdram rev. 1.1 mar. '99 - 7 - ac operating test conditions (v dd = 3.3v 0.3v , t a = 0 to 70 c) parameter value unit ac input levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 3.3v 1200 w 870 w output 50pf *1 v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 1.4v 50 w output 50pf *1 z0 = 50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit 1. the dc/ac test output load of km432s2030c-6/7 is 30pf. 2. the vdd condition of km432s2030c-6 is 3.135v~3.6v. note : 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. refer to the following clock unit based ac conversion table notes : operating ac parameter (ac operating conditions unless otherwise noted) parameter symbol version unit note -6 -7 -8 -10 clk cycle time t cc(min) 6 7 8 10 ns row active to row active delay t rrd(min) 12 14 16 20 ns 1 ras to cas delay t rcd(min) 18 18 18 20 ns 1 row precharge time t rp(min) 18 18 18 20 ns 1 row active time t ras(min) 42 49 48 50 ns 1 t ras(max) 100 us row cycle time t rc ( min ) 66 67 68 70 ns 1 last data in to row precharge t rdl(min) 2 clk 2,5 last data in to new col.address delay t cdl(min) 1 clk 2 last data in to burst stop t bdl(min) 1 clk 2 col. address to col. address delay t ccd(min) 1 clk 3 mode register set cycle time t mrs(min) 2 clk number of valid output data cas latency=3 2 ea 4 cas latency=2 1
km432s2030c cmos sdram rev. 1.1 mar. '99 - 8 - 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf)=1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. note : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -6 -7 -8 -10 unit note min max min max min max min max clk cycle time cas latency=3 t cc 6 1000 7 1000 8 1000 10 1000 ns 1 cas latency=2 - - 10 12 clk to valid output delay cas latency=3 t sac - 5.5 - 5.5 - 6 - 7 ns 1, 2 cas latency=2 - - - - - 7 - 8 output data t oh 2.5 - 2.5 - 2.5 - 2.5 - ns 2 clk high pulse width cas latency=3 t ch 2.5 - 3 - 3 - 3.5 - ns 3 cas latency=2 - clk low pulse width cas latency=3 t cl 2.5 - 3 - 3 - 3.5 - ns 3 cas latency=2 - input setup time cas latency=3 t ss 1.5 - 1.75 - 2 - 2.5 - ns 3 cas latency=2 - - input hold time t sh 1 - 1 - 1 - 1 - ns 3 clk to output in low-z t slz 1 - 1 - 1 - 1 - ns 2 clk to output in hi-z cas latency=3 t shz - 5.5 - 5.5 - 6 - 7 ns cas latency=2 - - - - - 7 - 8 symbol version unit -6 -7 -8 -10 cl 3 - 3 - 3 2 3 2 clk t cc(min) 6 - 7 - 8 10 10 12 ns t rrd(min) 2 clk t rcd(min) 3 - 3 - 3 2 2 2 clk t rp(min) 3 - 3 - 3 2 2 2 clk t ras(min) 7 - 7 - 6 5 5 4 clk t ras(max) 100 us t rc ( min ) 11 - 10 - 9 7 7 6 clk 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. 5. for -6/7/8/10, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv"
km432s2030c cmos sdram rev. 1.1 mar. '99 - 9 - simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap , a 9 ~ a 0 note register mode register set h x l l l l x op code 1,2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~ a 7 ) 4 auto precharge enable h 4,5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~ a 7 ) 4 auto precharge enable h 4,5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h v x 7 no operation command h x h x x x x x l h h h 1. op code : operand code a 0 ~ a 10 & ba 0 ~ ba 1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if both ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank b is selected. if both ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the data-in at the very clk (write dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2) notes : x
km432s2030c cmos sdram rev. 1.1 mar. '99 - 10 mode register field table to program modes register programmed with mrs address function a 10 /ap rfu a 9 w.b.l a 8 a 7 tm a 6 a 5 a 4 a 3 a 2 a 1 a 0 cas latency bt burst length a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 bt = 0 test mode type mode register set reserved reserved reserved 0 0 1 1 0 1 0 1 write burst length a 9 0 1 length burst single bit latency reserved reserved 2 3 reserved reserved reserved reserved cas latency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 burst type 0 1 bt = 1 burst length type sequential interleave 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 reserved reserved reserved full page 1 2 4 8 reserved reserved reserved reserved power up sequence 1. apply power and start clock, attempt to maintain cke= "h", dqm= "h" and the other pins are nop condition at the inputs. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. cf.) sequence of 4 & 5 is regardless of the order. the device is now ready for normal operation. note : 1. if a 9 is high during mrs cycle, "burst read single bit write" function will be enabled. 2. rfu (reserved for future use) should stay "0" during mrs cycle. full page length : x32 (256) ba 0 ~ ba 1 rfu
km432s2030c cmos sdram rev. 1.1 mar. '99 - 11 burst sequence (burst length = 4) initial address sequential interleave a 1 a 0 0 0 1 1 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0 burst sequence (burst length = 8) initial address sequential interleave 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 2 3 4 5 6 7 0 1 4 5 6 7 0 1 2 3 6 7 0 1 2 3 4 5 a 1 a 0 a 2 0 0 1 1 0 0 1 1 1 2 3 4 5 6 7 0 3 4 5 6 7 0 1 2 5 6 7 0 1 2 3 4 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 2 3 0 1 6 7 4 5 4 5 6 7 0 1 2 3 6 7 4 5 2 3 0 1 1 0 3 2 5 4 7 6 3 2 1 0 7 6 5 4 5 4 7 6 1 0 3 2 7 6 5 4 3 2 1 0
km432s2030c cmos sdram rev. 1.1 mar. '99 - 12 device operations nop and device deselect when ras , cas and we are high, the sdram performs no operation (nop). nop does not initiate any new operation, but is needed to complete operations which require more than sin- gle clock cycle like bank activate, burst read, auto refresh, etc. the device deselect is also a nop and is entered by asserting cs high. cs high disables the command decoder so that ras , cas , we and all the address inputs are ignored. power-up 1. apply power and start clock, attempt to maintain cke= "h", dqm= "h" and the other pins are nop condition at the inputs. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for both banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode reg- ister. cf.) sequence of 4 & 5 is regardless of the order. the device is now ready for normal operation. clock (clk) the clock input is used as the reference for all sdram opera- tions. all operations are synchronized to the positive going edge of the clock. the clock transitions must be monotonic between v il and v ih . during operation with cke high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well q perform and i cc specifications. clock enable (cke) the clock enable(cke) gates the clock onto sdram. if cke goes low synchronously with clock (set-up and hold time are the- same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is fro- zen as long as the cke remains low. all other inputs are ignored from the next clock cycle after cke goes low. when all banks are in the idle state and cke goes low synchronously with clock, the sdram enters the power down mode from the next clock cycle. the sdram remains in the power down mode ignoring the other inputs as long as cke remains low. the power down exit is synchronous as the internal clock is suspended. when cke goes high at least "1clk + t ss " before the high going edge of the clock, then the sdram becomes active from the same clock edge accepting all the input commands. bank addresses (ba0 ~ ba1) this sdram is organized as four independent banks of 524,288 words x 32 bits memory arrays. the ba 0 ~ ba 1 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. the bank addresses ba 0 ~ ba 1 are latched at bank active, read, write, mode register set and precharge operations. address inputs (a0 ~ a10) the 19 address bits are required to decode the 524,288 word locations are multiplexed into 11 address input pins (a 0 ~ a 10 ). the 11 bit row addresses are latched along with ras and ba 0 ~ ba 1 during bank activate command. the 8 bit column addresses are latched along with cas , we and ba 0 ~ ba 1 during read or write command.
km432s2030c cmos sdram rev. 1.1 mar. '99 - 13 mode register set (mrs) the mode register stores the data for controlling the various operating modes of sdram. it programs the cas latency, burst type, burst length, test mode and various vendor specific options to make sdram useful for variety of different applications. the default value of the mode register is not defined, therefore the mode register must be written after power up to operate the sdram. the mode register is written by asserting low on cs , ras , cas and we (the sdram should be in active mode with cke already high prior to writing the mode register). the state of address pins a 0 ~ a 10 and ba 0 ~ ba 1 in the same cycle as cs , ras , cas and we going low is the data written in the mode register. two clock cycles is required to complete the write in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. the mode register is divided into various fields depending on the fields of functions. the burst length field uses a 0 ~ a 2 , burst type uses a 3 , cas latency (read latency from column address) use a 4 ~ a 6 , vendor specific options or test mode use a 7 ~ a 8 , a 10 /ap and ba 0 ~ ba 1 . the write burst length is programmed using a 9 . a 7 ~ a 8 , a 10 /ap and ba 0 ~ ba 1 must be set to low for normal sdram operation. refer to the table for specific codes for vari- ous burst length, burst type and cas latencies. bank activate the bank activate command is used to select a random row in an idle bank. by asserting low on ras and cs with desired row and bank address, a row access is initiated. the read or write operation can occur after a time delay of t rcd (min) from the time of bank activation. t rcd is an internal timing parameter of sdram, therefore it is dependent on operating clock frequency. the minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t rcd (min) with cycle time of the clock and then rounding off the result to the next higher integer. the sdram has four internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of four banks simultaneously. also the noise generated during sensing of each bank of sdram is high, requiring some time for power supplies to recover before another bank can be sensed reliably. t rrd (min) specifies the minimum time required between activating different bank. the number of clock cycles required between different bank activation must be calculated similar to t rcd specification. the minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t ras (min). every sdram bank activate command must satisfy t ras (min) specification before a precharge command to that active bank can be asserted. the maximum time any bank can be in the active state is determined by t ras (max). the number of cycles for both t ras (min) and t ras (max) can be calculated similar to t rcd specification. burst read the burst read command is used to access burst of data on con- secutive clock cycles from an active row in an active bank. the burst read command is issued by asserting low on cs and cas with we being high on the positive edge of the clock. the bank must be active for at least t rcd (min) before the burst read com- mand is issued. the first output appears in cas latency number of clock cycles after the issue of burst read command. the burst length, burst sequence and latency from the burst read com- mand is determined by the mode register which is already pro- grammed. the burst read can be initiated on any column address of the active row. the address wraps around if the initial address does not start from a boundary such that number of out- puts from each i/o are equal to the burst length programmed in the mode register. the output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. the burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. the burst stop command is valid at every page burst length. burst write the burst write command is similar to burst read command and is used to write data into the sdram on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. by asserting low on cs , cas and we with valid column address, a write burst is initiated. the data inputs are provided for the initial address in the same clock cycle as the burst write command. the input buffer is deselected at the end of the burst length, even though the internal writing can be com- pleted yet. the writing can be completed by issuing a burst read and dqm for blocking data inputs or burst write in the same or another active bank. the burst stop command is valid at every burst length. the write burst can also be terminated by using dqm for blocking data and procreating the bank t rdl after the last data input to be written into the active row. see dqm operation also. device operations (continued)
km432s2030c cmos sdram rev. 1.1 mar. '99 - 14 dqm operation the dqm is used to mask input and output operations. it works similar to oe during read operation and inhibits writing during write operation. the read latency is two cycles from dqm and zero cycle for write, which means dqm masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. dqm operation is synchronous with the clock. the dqm signal is important during burst interruptions of write with read or precharge in the sdram. due to asynchronous nature of the internal write, the dqm operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. please refer to dqm timing diagram also. precharge the precharge operation is performed on an active bank by asserting low on cs , ras , we and a 10 /ap with valid ba 0 ~ ba 1 of the bank to be precharged. the precharge command can be asserted anytime after t ras (min) is satisfied from the bank active command in the desired bank. t rp is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing t rp with clock cycle time and rounding up to the next higher integer. care should be taken to make sure that burst write is completed or dqm is used to inhibit writing before precharge command is asserted. the maximum time any bank can be active is specified by t ras (max). therefore, each bank activate command. at the end of precharge, the bank enters the idle state and is ready to be activated again. entry to power down, auto refresh, self refresh and mode register set etc. is possible only when all banks are in idle state. auto precharge the precharge operation can also be performed by using auto precharge. the sdram internally generates the timing to satisfy t ras (min) and "t rp " for the programmed burst length and cas latency. the auto precharge command is issued at the same time as burst read or burst write by asserting high on a 10 /ap. if burst read or burst write by asserting high on a 10 /ap, the bank is left active until a new command is asserted. once auto precahrge command is given, no new commands are possible to that particular bank until the bank achieves idle state. both banks precharge both banks can be precharged at the same time by using pre- charge all command. asserting low on cs , ras , and we with high on a 10 /ap after all banks have satisfied t ras (min) require- ment, performs precharge on all banks. at the end of t rp after performing precharge to all the banks, both banks are in idle state. device operations (continued) auto refresh the storage cells of sdram need to be refreshed every 64ms to maintain data. an auto refresh cycle accomplishes refresh of a single row of storage cells. the internal counter increments automatically on every auto refresh cycle to refresh all the rows. an auto refresh command is issued by asserting low on cs , ras and cas with high on cke and we . the auto refresh com- mand can only be asserted with both banks being in idle state and the device is not in power down mode (cke is high in the previous cycle). the time required to complete the auto refresh operation is specified by t rfc (min). the minimum number of clock cycles required can be calculated by driving t rfc with clock cycle time and them rounding up to the next higher integer. the auto refresh command must be followed by nop's until the auto refresh operation is completed. all banks will be in the idle state at the end of auto refresh operation. the auto refresh is the preferred refresh mode when the sdram is being used for nor- mal data transactions. the auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms. self refresh the self refresh is another refresh mode available in the sdram. the self refresh is the preferred refresh mode for data retention and low power operation of sdram. in self refresh mode, the sdram disables the internal clock and all the input buffers except cke. the refresh addressing and timing are internally generated to reduce power consumption. the self refresh mode is entered from all banks idle state by asserting low on cs , ras , cas and cke with high on we . once the self refresh mode is entered, only cke state being low matters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. the self refresh is exited by restarting the external clock and then asserting high on cke. this must be followed by nop's for a minimum time of t rfc before the sdram reaches idle state to begin normal operation. if the system uses burst auto refresh during normal operation, it is recommended to use burst 4096 auto refresh cycles immediately after exiting in self refresh mode.
km432s2030c cmos sdram rev. 1.1 mar. '99 - 15 1) clock suspended during write (bl=4 1. clock suspend wr d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 clk cmd cke internal cke dq(cl2) dq(cl3) masked by cke 2) clock suspended during read (bl=4) d 0 not written 1) write mask (bl=4) 2. dqm operation wr d 0 d 1 d 3 d 0 d 1 d 3 clk cmd dqm dq(cl2) dq(cl3) masked bydqm 2) read mask (bl=4) rd q 0 q 2 q 3 q 1 q 2 q 3 masked by dqm dqm to data-in mask = 0 dqm to data-out mask = 2 hi-z hi-z 3) dqm with clock suspended (full page read) note 2 rd clk cmd cke dq(cl2) dq(cl3) q 0 q 4 q 7 q 8 q 2 q 3 q 6 q 7 q 1 hi-z hi-z hi-z hi-z hi-z hi-z dqm *note : 1. cke to clk disable/enable = 1clk. 2. dqm makes data out hi-z after 2clks which should masked by cke " l" 3. dqm masks both data-in and data-out. basic feature and function descriptions rd q 0 q 1 q 2 q 0 q 1 q 2 q 3 masked by cke q 3 suspended dout q 6 q 5
km432s2030c cmos sdram rev. 1.1 mar. '99 - 16 1) read interrupted by read (bl=4) 3. cas interrupt (i) clk cmd add note 1 rd rd a b qa 0 qb 1 qb 2 qb 3 qb 0 qa 0 qb 1 qb 2 qb 3 qb 0 tccd note 2 2) write interrupted by write (bl=2) 3) write interrupted by read (bl=2) wr wr a b tccd note 2 da 0 db 1 db 0 tcdl note 3 clk cmd add dq wr rd a b tccd note 2 tcdl note 3 da 0 qb 1 qb 0 da 0 qb 1 qb 0 dq(cl2) dq(cl3) *note : 1. by " interrupt", it is meant to stop burst read/write by external command before the end of burst. by " cas interrupt", to stop burst read/write by cas access ; read and write. 2. t ccd : cas to cas delay. (=1clk) 3. t cdl : last data in to new column address delay. (=1clk) dq(cl2) dq(cl3)
km432s2030c cmos sdram rev. 1.1 mar. '99 - 17 4. cas interrupt (ii) : read interrupted by write & dqm *note : 1. to prevent bus contention, there should be at least one gap between data in and data out. d 1 d 2 rd d 3 wr d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 rd wr rd wr hi-z hi-z rd wr q 0 d 1 d 2 d 3 d 0 note 1 hi-z (a) cl=2, bl=4 clk i) cmd dqm dq ii) cmd dqm dq iii) cmd dqm dq iv) cmd dqm dq (b) cl=3, bl=4 clk i) cmd dqm dq d 1 d 2 rd d 3 wr d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 rd wr rd wr d 1 d 2 d 3 d 0 rd wr rd wr d 1 d 2 d 3 d 0 hi-z ii) cmd dqm dq iii) cmd dqm dq iii) cmd dqm dq iv) cmd dqm dq q 0 note 1 hi-z
km432s2030c cmos sdram rev. 1.1 mar. '99 - 18 *note : 1. to prevent bus contention, dqm should be issued which makes at least one gap between data in and data out. 2. to inhibit invalid write, dqm should be issued. 3. this precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. 4. for -6/7/8/10, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" . from the next generation, trdl will be only 2clk for every clock frequency. 5. write interrupted by precharge & dqm d 0 d 1 d 2 clk cmd dqm dq masked by dqm wr pre d 3 note 3,4 note 2 6. precharge d 0 d 1 d 2 clk cmd dq wr pre d 3 1) normal write (bl=4) trdl note 1,4 2) normal read (bl=4) clk cmd dq(cl2) dq(cl3) rd pre q 0 q 1 q 2 q 3 q 0 q 1 q 2 q 3 1 2 *note : 1. t rdl : last data in to row precharge delay 2. number of valid output data after row precharge : 1, 2 for cas latency = 2, 3 respectively. 3. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of other activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same/another bank is illegal. 4. for -6/7/8/10, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" . from the next generation, trdl will be only 2clk for every clock frequency 7. auto precharge d 0 d 1 d 2 clk cmd dq wr d 3 1) normal write (bl=4) note 3,4 auto precharge starts 2) normal read (bl=4) clk cmd dq(cl2) dq(cl3) rd d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 note 3 auto precharge starts note 2
km432s2030c cmos sdram rev. 1.1 mar. '99 - 19 *note : 1. t rdl : 1 clk 2. t bdl : 1 clk ; last data in to burst stop delay. read or write burst stop command is valid at every burst length. 3. number of valid output data after row precharge or burst stop : 1, 2 for cas latency= 2, 3 respectiviely. 4. pre : all banks precharge if necessary. mrs can be issued only at all banks precharge state. 5. for -6/7/8/10, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" . from the next generation, trdl will be only 2clk for every clock frequency 8. burst stop & interrupted by precharge 3) read interrupted by precharge (bl=4) clk cmd dq(cl2) dq(cl3) rd pre q 0 q 1 q 0 q 1 1 2 9. mrs clk pre 1) mode register set 4) read burst stop (bl=4) clk cmd dq(cl2) dq(cl3) rd stop q 0 q 1 q 0 q 1 1 2 mrs act note 4 trp 2clk cmd d 0 d 1 d 2 clk cmd dq wr pre d 3 1) normal write (bl=4) trdl note 1,5 d 0 d 1 d 2 clk cmd dq wr stop d 3 2) write burst stop (bl=8) dqm dqm tbdl note 2 d 4 d 5 note 3
km432s2030c cmos sdram rev. 1.1 mar. '99 - 20 *note : 1. active power down : one or more banks active state. 2. precharge power down : all banks precharge state. 3. the auto refresh is the same as cbr refresh of conventional dram. no precharge commands are required after auto refresh command. during t rfc from auto refresh command, any other command can not be accepted. 4. before executing auto/self refresh command, all banks must be idle state. 5. mrs, bank active, auto/self refresh, power down mode entry. 6. during self refresh mode, refresh interval and refresh operation are perfomed internally. after self refresh entry, self refresh mode is kept while cke is low. during self refresh mode, all inputs expect cke will be don't cared, and outputs will be in hi-z state. for the time interval of t rfc from self refresh exit command, any other command can not be accepted. before/after self refresh mode, burst auto refresh cycle (4096 cycles) is recommended. 10. clock suspend exit & power down exit clk cke cmd rd 1) clock suspend (=active power down) exit tss clk cke cmd 2) power down (=precharge power down) exit note 1 note 5 internal clk nop tss note 2 internal clk 11. auto refresh & self refresh clk cmd 1) auto refresh & self refresh cke pre ar cmd note 4 trp trfc ? ? ? ? clk cmd 2) self refresh cke pre sr cmd note 4 trp trfc ? ? note 6 note 3 ? act
km432s2030c cmos sdram rev. 1.1 mar. '99 - 21 12. about burst type control at mrs a 3 = "0". see the burst sequence table. (bl=4, 8) bl=1, 2, 4, 8 and full page. at mrs a 3 = "1". see the burst sequence table. (bl=4, 8) bl=4, 8. at bl=1, 2 interleave counting = sequential counting every cycle read/write command with random column address can realize random column access. that is similar to extended data out (edo) operation of conventional dram. basic mode random mode sequential counting interleave counting random column access t ccd = 1 clk 13. about burst length control at mrs a 2,1,0 = "000". at auto precharge, t ras should not be violated. at mrs a 2,1,0 = "001". at auto precharge, t ras should not be violated. before the end of burst, row precharge command of the same bank stops read/write burst with row precharge. t rdl = 2 with dqm, valid dq after burst stop is 1, 2 for cas latency 2, 3 respectively. during read/write burst with auto precharge, ras interrupt can not be issued. basic mode interrupt mode 1 2 ras interrupt (interrupted by precharge) at mrs a 2,1,0 = "010". at mrs a 2,1,0 = "011". at mrs a 2,1,0 = "111". wrap around mode(infinite burst length) should be stopped by burst stop ras interrupt or cas interrupt 4 8 full page at mrs a 9 = "1". read burst =1, 2, 4, 8, full page write burst =1 at auto precharge of write, t ras should not be violated. t bdl = 1, valid dq after burst stop is 1, 2 for cas latency 2, 3 respectively using burst stop command, any burst length control is possible. before the end of burst, new read/write stops read/write burst and starts new read/write burst. during read/write burst with auto precharge, cas interrupt can not be issued. brsw burst stop cas interrupt random mode special mode
km432s2030c cmos sdram rev. 1.1 mar. '99 - 22 x x x ca, a 10 /ap ra a 10 /ap x op code x x x ca, a 10 /ap ca, a 10 /ap ra a 10 /ap x x x x ca, a 10 /ap ca, a 10 /ap ra a 10 /ap x x x x ca, a 10 /ap ca, a 10 /ap ra a 10 /ap x x x x ca, a 10 /ap ra, ra 10 x x x x ca, a 10 /ap ra, ra 10 x x x x ca ra a 10 /ap function truth table (table 1) current state cs ras cas we ba addr action note h l l l l l l l h l l l l l l l h l l l l l l l h l l l l l l l h l l l l l h l l l l l h l l l l l idle row active read write read with auto precharge write with auto precharge pre- charging nop nop illegal illegal row (& bank) active ; latch ra nop auto refresh or self refresh mode register access nop nop illegal begin read ; latch ca ; determine ap begin write ; latch ca ; determine ap illegal precharge illegal nop (continue burst to end --> row active) nop (continue burst to end --> row active) term burst --> row active term burst, new read, determine ap term burst, new write, determine ap illegal term burst, precharge timing for reads illegal nop (continue burst to end --> row active) nop (continue burst to end --> row active) term burst --> row active term burst, new read, determine ap term burst, new write, determine ap illegal term burst, precharge timing for writes illegal nop (continue burst to end --> precharge) nop (continue burst to end --> precharge) illegal illegal illegal illegal nop (continue burst to end --> precharge) nop (continue burst to end --> precharge) illegal illegal illegal illegal nop --> idle after t rp nop --> idle after t rp illegal illegal illegal nop --> idle after t rp l x x x ba ba ba x op code x x x ba ba ba ba x x x x ba ba ba ba x x x x ba ba ba ba x x x x ba ba x x x x ba ba x x x x ba ba ba x h h h l l l l x h h h h l l l x h h h h l l l x h h h h l l l x h h h l l x h h h l l x h h h l l x h h l h h l l x h h l l h h l x h h l l h h l x h h l l h h l x h h l h l x h h l h l x h h l h h x h l x h l h l x h l h l h l x x h l h l h l x x h l h l h l x x h l x x x x h l x x x x h l x h l 2 2 4 5 5 2 2 3 2 3 3 2 3 2 2 2 2 2 4
km432s2030c cmos sdram rev. 1.1 mar. '99 - 23 function truth table (table 1) current state cs ras cas we ba addr action note l h l l l l l l h l l l l h l l l l x x x x ca ra a 10 /ap x x x x x x x x x x x row activating refreshing illegal nop --> row active after t rcd nop --> row active after t rcd illegal illegal illegal illegal illegal nop --> idle after t rfc nop --> idle after t rfc illegal illegal illegal nop --> idle after 2 clocks nop --> idle after 2 clocks illegal illegal illegal x x x x ba ba ba x x x x x x x x x x x l x h h h l l l x h h l l x h h h l l x h h l h h l x h l h l x h h l x x x h l x h l x x x x x x x h l x x 2 2 2 2 mode register accessing *note : 1. all entries assume the cke was active (high) during the precharge clcok and the current clock cycle. 2. illegal to bank in specified state ; function may be iegal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba (and a 10 /ap). 5. illegal if any bank is not idle. abbreviations : ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge
km432s2030c cmos sdram rev. 1.1 mar. '99 - 24 function truth table (table 2) current state cs ras cas we addr action note x h l l l l x x h l l l l x x h l l l l l l x x x x x x x x x x x x x x x x x x x x x x x x ra x op code x x x x x self refresh invalid exit self refresh --> idle after t rfc (abi) exit self refresh --> idle after t rfc (abi) illegal illegal illegal nop (maintain self refresh) invalid exit power down --> abi exit power down --> abi illegal illegal illegal nop (maintain low power mode) refer to table 1 enter power down enter power down illegal illegal row (& bank) active enter self refresh mode register access nop refer to operations in table 1 begin clock suspend next cycle exit clock suspend next cycle maintain clcok suspend x x h h h l x x x h h h l x x x h h h l l l x x x x x x x h h l x x x x h h l x x x x h h l h l l x x x x x x x h l x x x x x h l x x x x x h l x h h l x x x x x 6 6 7 7 8 8 8 9 9 all banks idle *note : 6. cke low to high transition is asynchronous. 7. cke low to high transition is asynchronous if restarts internal clock. a minimum setup time 1clk + t ss must be satisfied before any command other than exit. 8. power down and self refresh can be entered only from the both banks idle state. 9. must be a legal command. abbreviations : abi = all banks idle, ra = row address cke (n-1) h l l l l l l h l l l l l l h h h h h h h h l h h l l x h h h h h l x h h h h h l h l l l l l l l l h l h l cke n all banks precharge power down any state other than listed above
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram single bit read-write-read cycle(same page) @cas latency=3, burst length=1 : don't care trcd *note 1 tss tsh trp tccd tss tsh trac tsac tslz toh tsh tss tss tsh tss tsh clock cke cs ras cas addr ba 0 ~ ba 1 a 10 /ap dq we dqm row active read write read row active precharge tch tcc tcl tras trc high tsh tsh tss tss *note 2,3 *note 2,3 *note 4 *note 4 *note 3 *note 3 *note 3 rb cc cb ca ra bs bs bs bs bs bs ra rb qc db qa *note 2,3 *note 2 *note 2
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram *note : 1. all input expect cke & dqm can be don't care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by ba0~ba1. 3. enable and disable auto precharge function are controlled by a10/ap in read/write command ba0 0 0 1 1 0 0 1 1 operation disable auto precharge, leave bank a active at end of burst. disable auto precharge, leave bank b active at end of burst. disable auto precharge, leave bank c active at end of burst. disable auto precharge, leave bank d active at end of burst. enable auto precharge, precharge bank a at end of burst. enable auto precharge, precharge bank b at end of burst. enable auto precharge, precharge bank c at end of burst. enable auto precharge, precharge bank d at end of burst. 4. a10/ap and ba0~ba1 control bank precharge when precharge command is asserted. a10/ap 0 1 ba1 0 1 0 1 0 1 0 1 ba0 0 0 1 1 active & read/write bank a bank b bank c bank d ba1 0 1 0 1 ba0 0 0 1 1 x precharge bank a bank b bank c bank d all banks a10/ap 0 0 0 0 1 ba1 0 0 1 1 x
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram power up sequence : don't care clock cke cs ras cas addr ba 0 a 10 /ap dq we dqm precharge auto refresh auto refresh mode register set row active ba 1 raa raa (all banks) (a-bank) trp trc high level is necessary high-z high level is necessary ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? trc key
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram read & write cycle at same bank @burst length=4 high : don't care *note : 1. minimum row cycle times is required to complete internal dram operation. 2. row precharge can interrupt burst on any cycle. [cas latency - 1] number of valid output data is available after row precharge. last valid output will be hi-z(t shz ) after the clcok. 3. access time from row active command. t cc *(t rcd + cas latency - 1) + t sac 4. ouput will be hi-z after the end of burst. (1, 2, 4, 8 & full page bit burst) 5. for -6/7/8/10, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" . from the next generation, trdl will be only 2clk for every clock frequency *note 1 trc trcd *note 2 trdl trdl tshz *note 4 tshz *note 4 toh trac *note 3 tsac tsac trac *note 3 toh ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock ra rb qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 db0 db1 db2 db3 ra ca rb cb we dqm row active (a-bank) precharge (a-bank) row active (a-bank) write (a-bank) precharge (a-bank) read (a-bank) *note 5 *note 5
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram page read & write cycle at same bank @burst length=4 high row active (a-bank) read (a-bank) write (a-bank) precharge (a-bank) : don't care *note : 1. to write data before burst read ends, dqm should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 4. for -6/7/8/10, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" . from the next generation, trdl will be only 2clk for every clock frequency read (a-bank) trcd *note 2 trdl *note 1 *note 3 tcdl qa0 qa1 qb0 qb1 qb2 qa0 qa1 qb0 qb1 dc0 dc1 dd0 dd1 dc0 dc1 dd0 dd1 write (a-bank) ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm ra ca cb cc cd ra *note 4
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram page read cycle at different bank @burst length=4 high row active (a-bank) read (a-bank) read (c-bank) precharge (b-bank) read (d-bank) : don't care *note : 1. cs can be don't cared when ras , cas and we are high at the clock high going dege. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same. row active (b-bank) *note 2 *note 1 row acive (c-bank) read (b-bank) precharge (a-bank) row active (d-bank) precharge (c-bank) precharge (d-bank) ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm qaa0 qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 qaa0 qaa1 qaa2 qbb0 qbb1 qbb2 qcc0 qcc1 qcc2 qdd0 qdd1 qdd2 raa rbb rcc rdd raa rbb caa rcc cbb rdd ccc cdd
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram page write cycle at different bank @burst length=4 high row active (a-bank) write (a-bank) row active (d-bank) write (d-bank) : don't care *note : 1. to interrupt burst write by row precharge, dqm should be asserted to mask invalid input data. 2. to interrupt burst write by row precharge, both the write and the precharge banks must be the same. 3. for -6/7/8/10, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" . from the next generation, trdl will be only 2clk for every clock frequency row active (b-bank) trdl row active (c-bank) precharge (all banks) tcdl write (b-bank) write (c-bank) *note 1 ba 0 ba 1 dq addr cas ras cs cke clock we dqm a 10 /ap raa rbb caa cbb rcc rdd ccc cdd rcc rdd raa rbb *note 2 daa0 daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dcc0 dcc1 ddd0 ddd1 ddd2 *note 3
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram read & write cycle at different bank @burst length=4 high raa row active (a-bank) write (d-bank) precharge (b-bank) : don't care *note : 1. t cdl should be met to complete write. read (a-bank) raa cdb rbc *note 1 tcdl rdb caa rac row active (d-bank) precharge (a-bank) read (b-bank) cbc rbb ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm qaa0 qaa1 qaa2 qaa3 qaa0 qaa1 qaa2 qaa3 ddb0 ddb1 ddb2 ddb3 ddb0 ddb1 ddb2 ddb3 qbc0 qbc1 qbc2 qbc0 qbc1
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram read & write cycle with auto precharge i @burst length=4 high row active (a-bank) 1. t rcd should be controlled to meet minimum t ras before internal precharge start. (in the case of burst length=1 & 2, brsw mode and block write) row active (b-bank) read with auto precharge (a-bank) auto precharge start point (b-bank) auto precharge start point (a-bank) write with auto precharge (b-bank) addr cas ras cs cke clock we dqm raa rbb caa rbb cbb *note : : don t care (cl=2) (cl=3) dq dq raa qaa0 qaa1 qaa2 qaa3 qaa0 qaa1 qaa2 qaa3 dbb0 dbb1 dbb2 dbb3 dbb0 dbb1 dbb2 dbb3 ba 0 a 10 /ap ba 1
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram read & write cycle with auto precharge ii @burst length=4 high row active (a-bank) : don't care *note: * when read(write) command with auto precharge is issued at a-bank after a and b bank activation. - if read(write) command without auto precharge is issued at b-bank before a bank auto precharge starts, a bank auto precharge will start at b bank read command input point . - any command can not be issued at a bank during trp after a bank auto precharge starts. row active (b-bank) read with auto pre charge (a-bank) write with auto precharge (a-bank) row active (a-bank) ba 0 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm qa0 qa1 qb0 qb1 qa0 qa1 qb0 qb1 ra rb ca ra rb ra cb qb2 qb3 read without auto precharge(b-bank) auto precharge start point (a-bank)* precharge (b-bank) da0 da1 da0 da1 qb2 qb3 ca ra ba 1
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram read & write cycle with auto precharge iii @burst length=4 high row active (a-bank) : don't care *note : * any command to a-bank is not allowed in this period. trp is determined from at auto precharge start point read with auto precharge (a-bank) auto precharge start point (a-bank) row active (b-bank) read with auto precharge (b-bank) ba 0 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qb0 qb1 qb2 qb3 ra ca ra cb rb rb * auto precharge start point (b-bank) ba 1
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram clock suspension & dqm operation cycle @cas latency=2, burst length=4 ra row active clock suspension read write dqm : don't care clock suspension read *note 1 tshz tshz write dqm write read dqm *note : 1. dqm is needed to prevent bus contention. ba 0 ba 1 dq addr cas ras cs cke clock we dqm a 10 /ap ra ca cb cc dc2 dc0 qb1 qb0 qa3 qa2 qa1 qa0
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram read interrupted by precharge command & read burst stop cycle @burst length=full page high row active (a-bank) : don't care *note : 1. at full page mode, burst is wrap-around at the end of burst. so auto precharge is impossible. 2. about the valid dqs after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing diagram. see the label 1, 2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of "full page write burst stop cycle". 3. burst stop is valid at every burst length. precharge (a-bank) burst stop read (a-bank) read (a-bank) 1 2 1 2 ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm qaa0 qaa1 qaa2 qaa3 qaa4 qaa0 qaa1 qaa2 qaa3 qaa4 qab0 qab1 qab2 qab3 qab4 qab5 qab0 qab1 qab2 qab3 qab4 qab5 raa caa cab raa
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram write interrupted by precharge command & write burst stop cycle @ burst length=full page row active (a-bank) burst stop write (a-bank) precharge (a-bank) : don't care write (a-bank) *note 2,4 tbdl *note : 1. at full page mode, burst is wrap-around at the end of burst. so auto precharge is impossible. 2. data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defined by ac parameter of t rdl. dqm at write interrupted by precharge command is needed to prevent invalid write. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 3. burst stop is valid at every burst length. 4. for -6/7/8/10, trdl=1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" . from the next generation, trdl will be only 2clk for every clock frequency. high trdl ba 0 ba 1 dq addr cas ras cs cke clock we dqm a 10 /ap daa0 daa1 daa2 daa3 daa4 dab0 dab1 dab2 dab3 dab4 dab5 raa caa cab raa
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram burst read single bit write cycle @burst length=2 high row active (a-bank) row active (c-bank) write with auto precharge (b-bank) : don't care *note : 1. brsw modes is enabled by setting a 9 "high" at mrs (mode register set). at the brsw mode, the burst length at write is fixed to "1" regardless of programmed burst length. 2. when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the burst-end cycle, so in the case of brsw write command, the next cycle starts the precharge. write (a-bank) *note 1 row active (b-bank) read (c-bank) read with auto precharge (a-bank) precharge (c-bank) *note 2 ba 0 ba 1 a 10 /ap cl=2 cl=3 dq addr cas ras cs cke clock we dqm daa0 daa0 qab0 qab1 qab0 qab1 dbc0 dbc0 qcd0 qcd1 qcd0 qcd1 raa caa rbb cab rcc cbc ccd rac raa rbb
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram active/precharge power down mode @cas latency=2, burst length=4 precharge power-down entry : don ?? t care *note : 1. both banks should be in idle state prior to entering precharge power down mode. 2. cke should be set high at least 1clk + tss prior to row active command. 3. can not violate minimum refresh specification. (64ms) *note 1 precharge tss *note 2 ba dq addr cas ras cs cke clock we dqm a 10 /ap tss tss ? ? ? ? ? ? ? ? ? ra ? ? ca ? ? ra ? ? qa0 qa1 qa2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? row active precharge power-down exit active power-down entry active power-down exit read tshz *note 3 ? *note 2
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram self refresh entry & exit cycle self refresh entry : don't care *note : to enter self refresh mode 1. cs , ras & cas with cke should be low at the same clcok cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don't care except for cke. 3. the device remains in self refresh mode as long as cke stays "low". cf.) once the device enters self refresh mode, minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system colck restart and be stable before returning cke high. 5. cs starts from high. 6. minimum t rc is required after cke going high to complete self refresh exit. 7. 4k cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst ref resh. *note 1 *note 7 ? ? ? ? ? ? ? ? ? ? ? ? hi-z ? ? ? ? ? ? hi-z ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? self refresh exit auto refresh tss *note 2 *note 3 *note 4 trcmin *note 6 *note 5 ba 0 ~ba 1 dq addr cas ras cs cke clock we dqm a 10 /ap ? ?
km432s2030c rev. 1.1 mar. '99 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cmos sdram mode register set cycle high mrs auto refresh : don't care *note : 1. cs , ras , cas , & we activation at the same clock cycle with address key will set internal mode register. 2. minimum 2 clock cycles should be met before new ras activation. 3. please refer to mode register set table. new command new command hi-z hi-z ? ? ? ? ? ? ? ? ? ? ? ? ? trc ? ? high mode register set cycle * all banks precharge should be completed before mode register set cycle and auto refresh cycle. auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 dq addr cas ras cs cke clock we dqm key ra *note 3 *note 1 *note 2
km432s2030c cmos sdram rev. 1.1 mar. '99 - 43 #1 1 1 . 7 6 0 . 2 0 0 . 4 6 3 0 . 0 0 8 0 . 0 2 0 0 . 5 0 ( ) 0.005 -0.001 +0.003 0.125 -0.035 +0.075 0 . 4 0 0 1 0 . 1 6 0 . 4 5 ~ 0 . 7 5 0 . 0 1 8 ~ 0 . 0 3 0 0.010 0.25 typ 0~8 c #86 #44 #43 0.010 0.05 min 0.008 0.21 0.002 0.05 0.004 0.10 max 0.024 0.61 ( ) 0.0197 0.50 0.047 1.20 max 0.039 1.00 0.004 0.10 0.891 22.62 max 0.875 22.22 0.004 0.10 0.20 +0.10 -0.03 86-tsop2-400f unit : millimeters package dimensions

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